| |
PA2AGA > TCPDIG 05.09.96 05:48l 145 Lines 6133 Bytes #-10896 (0) @ EU
BID : TCP_96_181B
Read: DG7DAH GUEST
Subj: TCP-Group Digest 96/181B
Path: DB0AAB<DB0KCP<DB0ZKA<DB0LX<DB0RBS<DB0SEL<DB0ZDF<DB0AIS<DB0NDK<DB0ACH<
DB0ACC<PI8DRS<PI8DAZ<PI8GCB<PI8MBQ<PI8VNW
Sent: 960905/0057Z @:PI8VNW.#ZH2.NLD.EU #:61786 [Hoek v Holland] FBB5.15c
From: PA2AGA@PI8VNW.#ZH2.NLD.EU
To : TCPDIG@EU
Received: from pa2aga by pi1hvh with SMTP
id AA17007 ; Thu, 05 Sep 96 00:35:21 UTC
Received: from pa2aga by pa2aga (NET/Mac 2.3.61/7.1) with SMTP
id AA00004159 ; Wed, 04 Sep 96 19:14:25 MET
Received: from pa2aga-10 by pa2aga with SMTP
id AA00004140 ; Wed, 04 Sep 96 19:07:58 MET
Received: from pa2aga-10 by pa2aga-10 (NET/Mac 2.3.61/7.1) with SMTP
id AA00005430 ; Wed, 04 Sep 96 19:07:54 MET
Date: Wed, 04 Sep 96 18:11:14 MET
Message-Id: <tcp_96_181B>
From: pa2aga
To: tcp_broadcast@pa2aga-10
Subject: TCP-Group Digest 96/181B
X-BBS-Msg-Type: B
same specific LPT port number, although there are conventions.
2.1 ADDRESSING CONVENTIONS
The video card's parallel port is normally at 3BCh. This address is
checked first by the BIOS, so if a port exists there, it will be LPT1.
The BIOS then checks at 378h, then at 278h. AFAIK there is no
standard address for a fourth port, and BIOSes only look for three.
3. DIRECT HARDWARE ACCESS
The port consists of three 8-bit registers at adjacent addresses in
the processor's I/O space. The registers are defined relative to
the I/O base address, and are at IOBase+0, IOBase+1, and IOBase+2
(for example if IOBase is 3BCh, then the registers are at 3BCh,
3BDh, and 3BEh). Always use 8-bit I/O accesses on these registers.
3.1 DATA REGISTER
The data register is at IOBase+0. It may be read and written (using
the IN and OUT instructions, or inportb() and outportb() or inp()
and outp()). Writing a byte to this register causes the byte value
to appear on pins 2 through 9 of the D-sub connector (unless the port
is bidirectional and is set to input mode). The value will remain
latched and stable until you write another value to the data
register. Reading this register yields the state of those pins.
7 6 5 4 3 2 1 0
* . . . . . . . D7 (pin 9), 1=High, 0=Low
. * . . . . . . D6 (pin 8), 1=High, 0=Low
. . * . . . . . D5 (pin 7), 1=High, 0=Low
. . . * . . . . D4 (pin 6), 1=High, 0=Low
. . . . * . . . D3 (pin 5), 1=High, 0=Low
. . . . . * . . D2 (pin 4), 1=High, 0=Low
. . . . . . * . D1 (pin 3), 1=High, 0=Low
. . . . . . . * D0 (pin 2), 1=High, 0=Low
3.2 STATUS REGISTER
The status register is at IOBase+1. It is read-only (writes will be
ignored). Reading the port yields the state of the five status input
pins on the parallel port connector at the time of the read access:
7 6 5 4 3 2 1 0
* . . . . . . . Busy . . (pin 11), high=0, low=1 (inverted)
. * . . . . . . Ack . . (pin 10), high=1, low=0 (true)
. . * . . . . . No paper (pin 12), high=1, low=0 (true)
. . . * . . . . Selected (pin 13), high=1, low=0 (true)
. . . . * . . . Error. . (pin 15), high=1, low=0 (true)
. . . . . * * * Undefined
3.3 CONTROL REGISTER
The control register is at IOBase+2. It is read/write:
7 6 5 4 3 2 1 0
* * . . . . . . Unused (undefined on read, ignored on write)
. . * . . . . . Bidirectional control, see below
. . . * . . . . Interrupt control, 1=enable, 0=disable
. . . . * . . . Select . . (pin 17), 1=low, 0=high (inverted)
. . . . . * . . Initialize (pin 16), 1=high, 0=low (true)
. . . . . . * . Auto Feed (pin 14), 1=low, 0=high (inverted)
. . . . . . . * Strobe . . (pin 1), 1=low, 0=high (inverted)
3.3.1 BIDIRECTIONAL CONTROL BIT
The bidirectional control bit is only supported on true bidirectional
ports - on other ports, it behaves like bits 7 and 6. On a proper
bidirectional port, setting this bit to '1' causes the outputs of the
buffer that drives pins 2 through 9 of the 25-pin connector to go into
a high-impedance state, so that data can be _input_ on those pins.
In this state, values written to the data register will be stored in
the latch chip, but not asserted on the connector, and reading the
data register will yield the states of the pins, which may be driven
by an external device without stressing or damaging the port driver.
Also note that on some machines, another port must be set correctly
to enable the bidirectional features, in addition to this bit.
I suspect this applies to machines with the parallel port integrated
on the motherboard as part of the motherboard chipset, but I do not
have details, sorry.
On some parallel port cards, bidirectional mode must be enabled by a
jumper setting. With this setting enabled, the bidirectional
control bit will be able to enable the bidirectional input mode.
3.3.2 INTERRUPT ENABLE BIT
DOS and BIOS do not use the interrupt facility of the parallel port
during printing. OS/2 versions up to 2.11 did use and rely on the
parallel port interrupt but OS/2 Warp does not by default.
For experimenters, the interrupt facility is useful as a general
purpose externally triggerable interrupt input.
The interrupt control bit controls a tristate buffer that drives the
IRQ line. Setting the bit to '1' enables the buffer, and an IRQ will
be triggered on each falling edge (high to low transition) of the Ack
signal on pin 10 of the 25-pin connector. Disabling the interrupt
allows other devices to use the IRQ line.
The actual IRQ number is either hardwired (by convention, the port at
3BCh uses IRQ7), or is jumper-selectable (IRQ5 is a common choice).
Sound cards, in particular, tend to use IRQ7 for their own purposes.
To use the IRQ you must also enable the interrupt via the interrupt
mask register in the interrupt controller, at I/O address 21h, and
your interrupt handler must send an EOI on exit. DOS technical
programming references have notes on writing interrupt handlers.
3.3.3 PRINTER CONTROL BITS
The bottom four bits are latched and presented on the parallel port
connector, much like the data register. Three of them are inverted,
so writing a '1' will output a low voltage on the port pin for them.
These four outputs are open collector outputs with pullup resistors,
so an external device can force them low without stressing the driver
To be continued in digest: tcp_96_181C
Read previous mail | Read next mail
| |
