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Q2.6: What standards are there for digital audio? What is AES/EBU?
What is S/P-DIF?
The "AES/EBU" (Audio Engineering Society / European Broadcast Union)
digital audio standard is probably the most popular digital audio
standard today. Most consumer and professional digital audio devices
(CD players, DAT decks, etc.) that feature digital audio I/O support
AES/EBU.
AES/EBU is a bit-serial communications protocol for transmitting
digital audio data through a single transmission line. It provides two
channels of audio data (up to 24 bits per sample), a method for
communication control and status information ("channel status bits"),
and some error detection capabilities. Clocking information (i.e.,
sample rate) is derived from the AES/EBU bit stream, and is thus
controlled by the transmitter. The standard mandates use of 32 kHz,
44.1 kHz, or 48 kHz sample rates, but some interfaces can be made to
work at other sample rates.
AES/EBU provides both "professional" and "consumer" modes. The big
difference is in the format of the channel status bits mentioned
above. The professional mode bits include alphanumeric channel origin
and destination data, time of day codes, sample number codes, word
length, and other goodies. The consumer mode bits have much less
information, but do include information on copy protection
(naturally). Additionally, the standard provides for "user data",
which is a bit stream containing user-defined (i.e.,
manufacturer-defined) data. According to Tim Channon, "CD user data is
almost raq CD subcode; DAT is StartID and SkipID. In professional
mode, there is an SDLC protocol or, if DAT, it may be the same as
consumer mode."
The physical connection media are commonly used with AES/EBU: balanced
(differential), using two wires and shield in three-wire microphone
cable with XLR connectors; unbalanced (single-ended), using audio coax
cable with RCA jacks; and optical (via fiber optics).
"S/P-DIF" (Sony/Philips Digital Interface Format) typically refers to
AES/EBU operated in consumer mode over unbalanced RCA cable. Note that
S/P-DIF and AES/EBU mean different things depending on how much of a
purist you are in the digital audio world; see the Finger article
below.
References:
Finger, Robert, "AES3-199X: The Revised Two Channel Digital Audio
Interface (DRAFT)", presented at the 91st Convention of the Audio
Engineering Society, October 4-8, 1991. Reprints: AES, 60 East 42nd
St., New York, NY, 10165.
[The above from Phil Lapsley, phil@ohm.Berkeley.EDU, and Tim Channon,
tchannon@black.demon.co.uk]
Q2.7: What is mu-law encoding? Where can I get source for it?
Mu-law (also "u-law") encoding is a form of logarithmic quantization
or companding. It's based on the observation that many signals are
statistically more likely to be near a low signal level than a high
signal level. Therefore, it makes more sense to have more quantization
points near a low level than a high level. In a typical mu-law system,
linear samples of 14 to 16 bits are companded to 8 bits. Most
telephone quality codecs (including the Sparcstation's audio codec)
use mu-law encoded samples.
Desktop Sparc machines come with routines to convert between linear
and mu-law samples. On a desktop Sparc, see the man page for
audio_ulaw2linear in /usr/demo/SOUND/man.
Craig Reese posted the source of similar routines to comp.dsp in
August '92. These are archived on
file://evans.ee.adfa.oz.au/pub/dsp/misc
You can get a G.721/722/723 package by email to teledoc@itu.arcom.ch,
with GET ITU-3022 as the *only* line in the body of the message. This
was originaly written by SUN, and includes ADPCM and ulaw encoders.
This is also available as:
file://svr-ftp.eng.cam.ac.uk/comp.speech/sources/G711_G722_G723.tar.Z
References:
CCITT Recommendation G.711 (very difficult to follow).
Michael Villeret, et. al, "A New Digital Technique for Implementation
of Any Continuous PCM Companding Law,", IEEE Int. Conf. on
Communications, 1973, vol. 1, pp. 11.12-11.17.
MIL-STD-188-113, "Interoperability and Performance Standards for
Analog-to-Digital Conversion Techniques," 17 February 1987.
"TI Digital Signal Processing Applications with the TMS320 Family",
pp. 169-198.
[From Joe Campbell; Craig Reese, cfreese@super.org; Sepehr Mehrabanzad,
sepehr@falstaff.dev.cdx.mot.com]
Q2.8: How can I do CD <-> DAT sample rate conversion?
CD players use a 44.1 kHz sample rate, whereas DAT uses a 48
kHz sample rate. This means that you must do sample rate
conversion before you can get data from a CD player directly
into a DAT deck.
[From Ed Hall, edhall@rand.org:]
For a start, look at "Multirate Digital Signal Processing"
by Crochiere and Rabiner (see FAQ section 1.1).
Almost any technique for producing good digital low-pass
filters will be adaptable to sample-rate conversion. 44.1:48
and vice-versa is pretty hairy, though, because the lowest
whole-number ratio is 147:160. To do all that in one go
would require a FIR with thousands of coefficients, of which
only 1/147th or 1/160th are used for each sample--the real
problem is memory, not CPU for most DSP chips. You could
chain several interpolators and decimators, as suggested by
factoring the ratio into 3*7*7:2*2*2*2*2*5. This adds
complexity, but reduces the number of coefficients required
by a considerable amount.
[From Lou Scheffer:]
Theory of operation: 44.1 and 48 are in the ratio 147/160.
To convert from 44.1 to 48, for example, we (conceptually):
1) interpolate 159 zeros between every input sample. This
raises that data rate to 7.056 MHz. Since it is
equivalent to reconstructing with delta functions, it
also creates images of frequency f at 44.1-f, 44.1+f,
88.2-f, 88.2+f, ...
2) We remove these with an FIR digital filter, leaving a
signal containing only 0-20 KHz information, but still
sampled at a rate of 7.056 MHz.
3) We discard 146 of every 147 output samples. It does
not hurt to do so since we have no content above 24 KHz.
In practice, of course, we never compute the values of
the samples we will throw out.
So we need to design an FIR filter that is flat to 20 KHz,
and down at least X db at 24 K,I]ðÿ'Aé3IV3II¨}ò=Æ3IV3Ight think about 100 db, since the max signal size
is roughly +-32767, and the input quantization +- 1/2, so we
know the input had a signal to broadband noise ratio of 98
db at most. However, the noise in the stopband
(20KHz-3.5MHz) is all folded into the passband by the
decimation in step 3, so we need another 22 db (that's 160
in db) to account for the noise folding. Thus 120 db
rejection yields a broadband noise equal to the original
quantizing noise. If you are a fanatic, you can shoot for
130 db to make the original quantizing errors dominate, and
a 22.05 KHz cutoff to eliminate even ultrasonic aliasing.
You will pay for your fanaticism with a penance of more
taps, however.
For more details, a technical report (the author's name is
missing, if you know who - let me know!), is available is
LaTeX source form as
file://evans.ee.adfa.oz.au/pub/dsp/cd-rate-convert.tex
and in PostScript as
file://evans.ee.adfa.oz.au/pub/dsp/cd-rate-convert.ps
There's a free implementation of Julius O. Smith III and someone
else's "bandwidth-limited interpolation" rate conversion algorithm.
The paper available as
file://ccrma-ftp.stanford.edu/pub/DSP/Tutorials/BandlimitedInterpolation.eps.Z
explains the algorithm. The source code in
file://netcom.com/pub/thinman/resample.01.Z
file://netcom.com/pub/thinman/resample.02.Z
file://netcom.com/pub/thinman/kaiser.c
implements the algorithm. It all works quite well.
Q3.1: What are the available DSP chips and chip architectures?
{ This is based on a woefully inadequate databook collection. Anyone want
to add to this list? Manufacturers want to submit anything? }
The "big four" programmable DSP chip manufacturers are Texas
Instruments, with the TMS320 series of chips; Motorola, with the
DSP56000, DSP56100 and DSP96000 series; AT&T, with the DSP16 and DSP32
series; and Analog Devices, with the ADSP2100 series. A good overview
of prorammable DSP chips is published periodically in EDN magazine.
The most recent version is from Sep. 17, 1992, pp. 90-141.
Here's a less ambitious chip breakdown by manufacturer:
Texas Instuments:
TMS320C1x: family of low cost fixed-point DSP's; 16 bit data, 32 bit
registers; Various RAM and ROM configurations; 16 bit I/O bus, serial
ports.
TMS320C25: 50MHz fixed-point DSP; 16 bit data, 32 bit registers; 12.5
MIPS @ 50MHz.
TMS320C30: 27/33/40 MHz floating point DSP; 32 bit floating point, 24
bit fixed point data, 40 bit registers; DMA controller; dual serial
ports; some support for multi-processor arrays.
TMS320C31: version of C30 minus peripheral bus, one serial port, and
the 4Kx32 internal ROM. ~$20, 132 pin PQFP.
TMS320C40: 40/50 MHz floating point DSP; extensive parallel processing
support through 6 buffered byte-wide 20 Mb/s links and 6 channel DMA;
cache.
TMS320C50: enhanced TMS320C25 (double throughput); low overhead
looping; 10 Kwords SRAM on chip.
Motorola:
DSP56001: 20.5, 27, or 33 MHz 24-bit fixed point DSP. 24 bit data
bus, 16 bit address bus, 56 bit accumulators (2), host interface port,
serial ports (2), general purpose I/O pins, timer. Harvard
architecture. 512 words program RAM, 32 words bootstrap ROM, 512
words data RAM, 512 words data ROM on chip. Available in PGA, CQFP or
PQFP packaging.
DSP56000: Mask-programmed version of DSP56001, same peripherals and
data memories, 3.75k words program ROM on chip.
DSP56002: modular DSP based on new 24-bit DSP56k core, a superset of
the DSP56001 architecture with On-Chip Emulation (OnCE) debug port,
clock PLL and improved bus arbitration. Has four cycle double
precision multiply and support for block floating point. Same memory
as in DSP56001, except for 64 words bootstrap ROM. Host interface
port, serial ports (2), general purpose I/O pins, programmable 24-bit
timer, non-maskable interrupt. Low power fully static design, no
minimum clock frequency requirement. Available at 40 MHz (5V supply)
in PGA and CQFP packaging.
DSP56L002: Low-power version of the DSP56002 offering identical
performance as the DSP56002 but at 3.3V. Available in PQFP.
DSP56004: modular DSP, same 24-bit DSP56k core as in
DSP56002. Targeted to consumer digital audio applications. Has
On-Chip Emulation (OnCE) debug port, clock PLL, serial host interface
(I2C and SPI), four general purpose I/O pins, two stereo serial audio
receivers (I2S/Sony), three stereo serial audio transmitters
(I2S/Sony), external SRAM/DRAM memory interface with 8-bit data bus.
Low power fully static design, no minimum clock frequency requirement.
Available at 40 MHz (5V supply) in 80-pin QFP package.
DSP56156: 40, 50, or 60 MHz fixed point DSP; 16 bit data bus, 40 bit
accumulators (2), host interface port, serial ports (2), timer, OnCE
debug port, clock PLL, 14 bit sigma-delta voice band CODEC, 2K words
program RAM, 2K words data RAM on chip.
DSP56166: 60 MHz fixed point DSP; 16 bit data bus, 40 bit
accumulators (2), host interface port, CODEC, 16-bit timer and
event counter, serial ports (2), OnCE debug port, clock PLL, 4K
data RAM, 2K program RAM. Available in PQFP.
DSP96002: IEEE format floating point DSP; two complete 32 bit data and
address buses; Harvard architecture. 1k words program RAM, 64 words
bootstrap ROM, 1k words data RAM, 1k words data ROM, host interface
ports (2). Available in 33 MHz or 40 MHz in 223-pin PGA packaging.
[The above from Sergio Liberman, sergio@msil.sps.mot.com ]
AT&T:
DSP 16 FAMILY: DSP16A, $22.60; DSP1610, $91; DSP1616, $35.70 16 bit
fixed point DSPs. The DSP16A has a 25ns cycle time while the 16C has
an ADC and DAC on chip. The C-version also has a 4-pin JTAG interface.
The 1610/1616 are enhanced versions intended for cellular phone use.
The chips use separate on-chip 16-bit program- and data buses. The A
and C versions have 12k x 16-bit program ROM and a 2k x 16-bit
data-RAM while featuring parallell and serial I/O.
DSP 32Ce bus can
be accessed four times and each internal memory two times per
cycle. The 3210, along with the VCOS operating system is intended for
use on the mother board of personal computers and workstations where
it shares memory with the host. The 32C has three 512 x 32-bit RAM:s
while the 3210 has two 1k x 32-bit RAMs and a 256P3207: 32-bit floating point with four 40-bit floating-point
accumulators and twenty-two general purpose 32-bit fixed point
registers. Single 32-bit (4G-byte) linear memory space. Support for
byte, 16-bit word, and 32-bit word accesses. Big/little endian
interface. C-like assembly language. Up to four memory accesses per
instruction. VCOS operating system allows sharing of host memory
(e.g. mother-board or local-bus board) or operation out of inexpensive
DRAM (e.g. ISA board). Two 1k x 32-bit RAMs and a 256 x 32-bit boot
ROM. Serial I/O, timer, DMA-controller. The DSP3207 is functionally
equivalent to the DSP3210 except it lacks the serial I/O and
associated DMA controller and has been designed for low power
dissipation. DSP3210 available at 55MHz/5V and 66MHz/5V. DSP3207
available at 55MHz/5V and 66MHz/5V and 40MHz/3V.
Analog Devices: ADSP-2100: 40 and 50Mhz fixed point DSP (10
MIPS, 12.5MIPS). 16 bit operations with 40-bit multiply-accumulate.
No on chip memory except for a 16 word instruction cache. Off chip
harvard architecture. PGA and PQFP packages.
ADSP-2101: Derived from ADSP-2100; 16 bit operations with 40-bit MAC
register. Extras include on chip memory of 2Kx24 program memory
instruction/data RAM and 1Kx16 data memory RAM, 16-bit timer, two
serial ports, low power state. PGA, PLCC, PQFP packages. Fastest
speed grade in production is 20.0 MHz (20.0MIPS).
ADSP-2102: RAM/ROM version of 2101; user selects how much of the 2kx24
program memory is mask ROM.
ADSP-2103: 3.3V version of the 2101 running at 10.24MHz (10.24 MIPs).
PLCC, PQFP packages.
ADSP-2105: 13.824Mhz (13.824MIPS) low cost fixed point DSP with 1
serial port, timer and 1kx24 instruction/data RAM in program memory
space, and 512 word data RAM in data memory space. Architecture and
instruction set identical to ADSP-2101. Pin compatible with 2101.
PLCC package only (can use standard 68 pin plcc socket). This
processor sells for US $9.90 in any quantity.
ADSP-2115: Architecture and pinout same as ADSP-2101, but 1K program
memory RAM, 1/2K data memory RAM with 2 serial ports, interval timer
etc. PLCC, PQFP, and TQFP packages. Available in 13.8MHz, 16.67MHz
and 20MHz (13.8, 16.67, 20 MIPs)
ADSP-2161: Architechture and pinout same as ADSP-2101 but with 8Kx24
mask program memory ROM, 1/2K data memory RAM with two serial ports,
interval timer etc. PLCC, PQFP packages. Availble in 16.67MHz
(16.67MIPs)
ADSP-2162: 3.3V version of the 2161 running at 10.24MHz
(10.24MIPs). PLCC and PQFP packages.
ADSP-2163: Architechture and pinout same as ADSP-2101 but with 4Kx24
mask program memory ROM, 1/2K data memory RAM with two serial ports,
interval timer etc. PLCC, PQFP packages. Availble in 16.67MHz
(16.67MIPs)
ADSP-2164: 3.3V version of the 2163 running at 10.24MHz
(10.24MIPs). PLCC and PQFP packages.
ADSP-2111: Adds a 8/16bit host interface port to ADSP-2101 architecure
allowing interface to Intel or Motorola style microprocessors. 13,
16.67 and 20 MIPs speeds available. PGA and PQFP packages.
ADSP-21msp50: ADSP-2111 with an on chip a/d and d/a interface (65dB
SNR) Additional low power modes allow CMOS standby (<100uA). 100-lead
PQFP package.
ADSP-2171: Speed & feature enhanced ADSP-2100 family processor with
instruction set extensions, 2Kx24 program memory RAM, 2Kx16 data
memory RAM, 8K words Mask programmable ROM (disablable) 2 serial
ports, host interface port, CMOS standby powerdown mode, 1/2X
instruction clock(i.e. 38.46ns cycle time from 13.0MHz clock to get
26MIPs performance) PQFP & TQFP packages. Faster version soon.
ADSP-21020: 20/25/33 MHz floating-point DSP; Supports 32-bit fixed
point, IEEE format 32-bit floating point, and 40-bit floating point;
40-bit registers plus two 80-bit fixed-point multiply-accumulators;
Harvard arch. with 32 word instruction cache allows two data accesses
in a single cycle; IEEE 1149.1 JTAG boundry scan; 33.3 MIPS @ 33.3
MHz.
ADSP21010: Slower inexpensive version of '020 (16 MHz). Limited to
32-bit fixed and floating point.
All of the processors (except the 2100 & 2171) use a 1X instruction
clock and an on chip PLL to generate an internal 4X clock. The 2171
uses a 1/2X instruction clock and an on chip PLL to generate an
internal 4X clock. All processors have an extended Harvard
architecture which allows two data fetches and an instruction fetch
every cycle in parallel with an alu or mac operation.
Processors with internal memory support booting from inexpensive 8 bit
EPROMS. All processors include hardware support for zero overhead
looping, modulo addressing, single cycle context switch, and bit
reversal addressing. All instructions, even those which access
external memory can complete in 1 cycle.
Q3.2: Software for Motorola DSPs.
Q3.2.1: Where can I get a free assembler for the Motorola DSP56000?
A free assembler for the Motorola DSP56000 exists, thanks to Quinn
Jensen, jensenq@qcj.icon.com. The current version is 1.1, and
it is posted to alt.sources, so look for it on mirrors of that
newsgroup (like wuarchive.wustl.edu).
Q3.2.2: Where can I get a free C compiler for the Motorola DSP56000?
There are two separate compiler sources for the Motorola DSP56000. One
is the port of gcc 1.40 done by Andrew Sterian (asterian@eecs.umich.edu) and
the other is a port of gcc 1.37.1 done by Motorola and returned to the
FSF. Andrew's port has bowed to Motorola's version. Both may be
portable to gcc2.x.x with some effort required. Neither of these comes
with an assembler, but you can get a free DSP56000 assembler elsewhere
(see Q3.2.1 above).
The Motorola gcc source is available for FTP from:
nic.funet.fi ~pub/ham/dsp/dsp56k-tools/dsp56k-gcc.tar.Z
evans.ee.adfa.oz.au pub/micros/56k/g56k.tar.Z
Andrew Sterian (asterian@eecs.umich.edu) ported GCC to the DSP56100
family. Both this compiler and the previous incarnation are archived
on wuarchive.wustl.edu (in the usenet/alt.sources directory) amongst
other places. This is no longer the only DSP56100 compiler - Motorola
also has compilers for each of their DSP families.
Q3.2.3: Where can I get algorithms and libraries for Motorola DSPs?
What is the number for the Motorola DSP BBS?
Motorola runs "Dr. Bub", a bulletin board for DSPs containing source code
for various libraries and algorithms. You can call it at (512) 891-3771
(9600, 4800, 2400, 1200 bps) or (512) 891-3773 (2400/1200/300 bps).
Format is 8 data bits, no parity, 1 stop bit). Log in as "guest" to
browse the system, or you can open an account by entering "new" at the
account name prompt. [John Fisher, johnf@dsp.sps.mot.com]
Alternatively, Dr. BuB is mirrored on the following sites:
calvin.stanford.edu (36.14.0.43) in /motorola
bode.ee.ualberta.ca (129.128.16.96) in /pub/dos/motorola
nic.funet.fi (128.214.6.100) in /pub/misc/motorola
doc.ic.ac.uk (146.169.3.7) in
/computing/systems/motorola/digital-signal-processing/dr.bub.sources
Also try nic.funet.fi in /pub/ham/dsp for a lot of good stuff on
communications uses, including some hardware.
ccrma-ftp.stanford.edu also has a variety of DSP code (much of it NeXT
specific, see below), including the following for the DSP56000:
pub/clm.tar.Z "CLM", a package aimed mainly at composers doing
computer music in Common Lisp, but includes a Lisp
56000 assembler, debugger, loader, large libraries of
DSP56000 routines useful in computer music, and
a compiler from a subset of Common Lisp to
DSP56000 code. [bil@ccrma.stanford.edu]
Q3.2.4: Where can I get NeXT-compatible Motorola DSP56001 code?
Try the following from ccrma-ftp.Stanford.EDU:
DSP programs for the NeXT platform:
pub/DSP/resample.tar.Z Audio sampling-rate conversion and FIR
filter design.
pub/DSP/ResoLab2.1.tar.Z Interactive filter instrument; sources now
included, online help.
pub/DSP/Spectro.Z Spectrum analysis tool, with source code.
pub/DSP/WaveFormEditor.tar.Z Jean Laroche's real-time waveform editor,
with DAJ's additions.
DSP programming examples for the NeXT platform:
pub/DSP/dsp_dma_stream.tar.Z Fast DSP DMA programming example (two-way DMA).
pub/DSP/JeanLaroche.tar.Z Low-level sound and DSP programming examples
and docs.
[bil@ccrma.Stanford.EDU]
Q3.3: Software for Texas Instruments DSPs.
Q3.3.1: Where can I get free algorithms or libraries for TI DSPs?
What is the number for the TI DSP BBS?
nic.funet.fi has some old, apparently public domain, assembler and
related tools from TI for the TMS320 family. [Antti-Pekka Virtanen,
antsu@utu.fu]
The TI DSP bulletin board is at (713) 274-2323 (300, 1200, 2400, or 9600 bps;
8 data, 1 stop, no parity).
The TI DSP bulletin board is mirrored on ftp://ti.com/pub/mirrors/tms320bbs , and on
file://evans.ee.adfa.oz.au/mirrors/tibbs. The TI site is the official one, but has
no user contributed software. The file:
file://evans.ee.adfa.oz.au/mirrors/tibbs/00README
provides further guidance.
Please restrict FTP session to outside of 8 am to 6 pm local
time (10 pm to 8 am GMT).
[Brad Hards, bradh@ee.adfa.oz.au]
{ If anyone knows of any other sources for TI DSP software, please let
us know at comp-dsp-faq@ohm.Berkeley.EDU. Thanks! }
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