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DK6JU > DSP 17.06.96 22:07l 413 Lines 13331 Bytes #-10684 (0) @ DL
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Read: DC4MG DK8RW DJ2TK DL1EEC DG9ALL DK5RAS GUEST
Subj: C50-CPU-BUGs
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Sent: 960617/1720z @:DB0IZ.#NRW.DEU.EU [JO31NE, Op: DL6EE] $:176607DB0IZ
de DK6JU @ DB0IZ.#NRW.DEU.EU (Michael)
to DSP @ DL
Hallo DSP'ler,
wer schon mal Software für den C50-DSK von TI entwickelt hat, wird
festgestellt haben, daß die Programme nicht auf jedem DSK laufen.
Ursache dafür scheinen Änderungen in der C50 CPU zu sein. Die
original Fehlerlisten von TI sind im folgenden Abgedruckt.
Der Übergang von der CPU Rel. 1.x auf die CPU Rel. 2.x erfolgte
anscheinen bei den DSKs, die ab Ende 95 ausgeliefert wurden. Achtung:
die Änderungen im Layout und der Schaltung des DSK dienen der
Verbesserung der EMV und haben n i c h t s mit dem CPU-Release zu
tuen!
Die Probleme, die mir aufgefallen sind, betreffen die Ansteuerung des
AIC durch die serielle Schnittstelle. Manche Programme, die auf der alten
CPU laufen geben auf der neuen CPU nur noch einen Knacks von sich und
tuen anscheinend nichts mehr. Bei genauerer Analyse stellt man fest,
daß die Programm selbst noch laufen, aber die Interruptroutinen für
die serielle Schnittstelle nicht mehr ablaufen.
Um diese Probleme zu vermeiden, muß man sorgfältig darauf achten, daß
man jeden vom AIC geschickten Wert auch aus dem DRR-Register
ausliest. Wenn man das nur einmal versäumt (z.B. weil man den Wert
nicht braucht), werden k e i n e Receive-Interrupts (RINT) mehr
erzeugt (bis man wieder DRR ausliest)!
Das führt je nach Struktur des Programms zum völligen
Stillstand des Programms oder es werden halt keine neuen Werte mehr
eingelesen. Entsprechendes gilt für den Transmit-Interrupt (XINT):
wenn man nach einem XINT keinen neuen Wert in das DXR-Register
schreibt, werden keine XINTs mehr erzeugt.
Beim alten CPU-Releasestand traten in diesen Fällen keine Probleme
auf, weil jeder FSR/FSX-Impuls einen Interrupt auslöste, unabhängig vom
overflow/underflow-Status von DRR/DXR.
vy 73 Michael, DK6JU
Hier die ERRATA-SHEETS von TI:
TMS320C5xPQ SILICON ERRATA
Rev 1.x Silicon (Document Revision 1.2)
Last Modified:06/08/92
The following problems exist in the TMS320C50PQ, the
TMS320C51PQ, and the TMS320C53PQ (The PQ is the Plastic
Quad Flat Pack package and should be distinguished from the
ceramic HQ package). Each problem is described and an
appropriate work around is presented. In addition, the
revision in which the problem is fixed or will be fixed is
included.
PROBLEM 1:
The underflow and overrun error flags on serial port #1 and
serial port #2 (TDM and non-TDM mode), XSREMPTY and RSRFULL,
are non-functional. These flags should not be used to detect
any error condition.
On the receive side of the serial port #1 (and the serial
port #2 in non-TDM mode), RSR (TRSR) register contents are
copied to DRR (TDRR) register each time RSR (or TRSR) has
shifted in a full word (or byte) and the previous contents
of DRR (or TDRR) have already been read. This is normal
device operation. However, if the current DRR (or TDRR)
contents have not been read and RSR (or TRSR) has received
new word then RSR (or TRSR) to DRR (TDRR) transfer will
still take place if external FSR line strobes, thus
overwriting DRR. The receive interrupt would also be
generated at the same time. According to the serial port
specs, RSR (or TRSR) to DRR (or TDRR) transfer should not
have taken place in this receive over-run condition.
On the transmit side the operation of the serial port is
according to spec except for the non-functionality of the
XSREMPTY flag.
For the Continuous Mode, both receive and transmit sides,
the silicon behaves as described above.
WORK AROUND 1:
Note that both the serial ports (TDM or non-TDM) behave
according to the specs except under receive over-run and
transmit under-flow conditions. The user should either avoid
these conditions or understand the ramifications of it.
WILL FIX IN SILICON REVISION 2.x
PROBLEM 2:
A RPT instruction located within two words of the end of a
repeat block will cause the block repeat counter BRCR and
the repeat counter RPTC to be corrupted.
RPTB END_LOOP-1
.
.
RPT TIMES
NOP ;Any repeatable C5X instruction
NOP ;Any valid C5X instruction
END_LOOP
WORK AROUND 2:
Place a NOP between the repeated instruction and the end of
the repeat block.
RPTB END_LOOP-1
.
.
RPT TIMES
NOP ; Any repeatable instruction
NOP ; Any valid C5X instruction
NOP ; Added as bug workaround
END_LOOP
WILL FIX IN SILICON REVISION 2.x.
PROBLEM 3:
An XC instruction located at the end of a repeat block with
k=2 will cause the block repeat counter BRCR to not
decrement if the condition is false.
RPTB END_LOOP-1
.
.
XC 2, cond
NOP ; Could be 1 2-word or 2
NOP ; 1-word C5X instructions.
END_LOOP
WORK AROUND 3:
Place a NOP between the instruction and the end of the
repeat block.
RPTB END_LOOP-1
.
.
XC 2, cond
NOP ; Could be 1 2-word or 2
NOP ; 1-word C5X instructions
NOP ; Added as bug workaround
END_LOOP
WILL FIX IN SILICON REVISION 2.x.
PROBLEM 4:
When coming out of HOLD (HOLDA_ goes high) if the first
action is an external memory write, the STRB_ signal will go
active one cycle early for that write. There is no problem
in this situation with the first read or any subsequent
accesses. This problem does not affect any of the other
memory interface signals.
WORK AROUND 4:
This is a hardware bug and has no software workarounds.
Even though STRB_ becomes active one cycle early, WE_ only
becomes active as specified and data will be valid on the
bus when WE_ is active. If WE_ is used to write data into
the target devices (memory or I/O), then correct data would
be written.
WILL FIX IN SILICON REVISION 2.x.
PROBLEM 5:
The I/O space addresses from 20h to 4Fh and from 80h to FFh
are not decoded. Thus instructions using these port
addresses will not function properly. There is no problem
with the sixteen memory-mapped port addresses in the range
50h to 5Fh. The following map identifies the problem
addresses in I/O space.
I/O
0000h _________
| |
| Valid |
001Fh| |
0020h|---------|
| Invalid |
004Fh|---------|
0050h| |
| Valid |
007Fh| |
0080h|---------|
| Invalid |
00FFh|---------|
0100h| |
| Valid |
| |
FFFFh|_________|
C5X I/O Space Map
WORK AROUND 5:
Avoid using the I/O space port addresses cautioned above.
WILL FIX IN SILICON REVISION 2.x.
COMPATIBILITY NOTE:
The frame synchronization pulse of the C5X is an active high
signal that marks the beginning of a serial port transfer.
Thus when coming out of serial port or device reset, the FSX
pin (if configured as an input) should be low. The
following problem is discussed because of compatibility
issues with certain parts such as the TLC320XX Analog
Interface Chip (AIC).
PROBLEM 6:
If the transmit frame sync (FSX or TFSX) pin is configured
as input on serial port #1 (or serial port #2 in non-TDM
mode) and it is kept high when serial port is taken out of
reset then the first word shifted out on DX (or TDX) line
may be random. This may happen because the DXR to XSR (or
TDXR to TXSR) transfer does not take place under this
condition when the serial port is taken out of reset and the
uninitialized contents of XSR (or TXSR) are shifted out at
the falling edge of FSX (or TFSX). Note that in this case,
the first word written to DXR (or TDXR) by the user's code
will be transmitted as the second word on DX (or TDX) line.
WORK AROUND 6:
In most serial port interfaces, transmit frame sync input is
kept low (or inactive) until the serial port is initialized.
For such cases, the above problem will not be relevant.
However, in case of AIC (TLC320xx) interface, FSX (or TFSX)
will be driven high by AIC during periods of inactivity. If
a power-up reset is used on AIC then it is likely that the
FSX (or TFSX) line will be high when the serial port is
taken out of reset. Since a random data transfer from 'C5x
to the AIC can potentially modify AIC's mode of operation,
it is recommended that the 'C5x has control over the AIC reset
line. The following code illustrates the AIC initialization
using XF to control AIC reset line:
.
.
.
* initialize serial port
*
lacc #0000000000001000b ; initialize serial port
sacl spc
lacc #0000000011001000b ; take it out of reset
sacl spc
zac
sacl dxr ; clear first int
rpt #100 ; wait a few cycles
nop
clrc xf ; put AIC in reset
rpt #N ; N depends on min AIC reset
nop ; pulse width
setc xf ; take AIC out of reset
splk #020h,imr
; enable xint for aic init
splk #0ffffh,ifr
clrc intm ; enable interrupts
.
.
.
WILL MODIFY (MAKE NON-RANDOM) IN SILICON REVISION 2.x
TMX320C5x silicon errata
Rev 2.x silicon (Document Revision 2.0)
Last Modified: 10/08/93
Silicon revision 2.x of C5X that includes TMx320C50, TMx320C51,
TMx320C52, TMx320C53, and TMx320C53SX have the following problems.
Each problem is described and an appropriate work around is
suggested.
Problem 1: The OUT instruction may corrupt some memory map registers.
The I/O space addresses from 20h to 4Fh are not properly decoded.
Whenever the case of writing to this I/O block occurs the internal
data memory from 20h to 4Fh is also accessed. Thus the OUT
instruction using these port addresses will also overwrite the memory
map registers that between 20h and 4Fh. However, there is no problem
with the sixteen memory-mapped port addresses in the range 50h to
5Fh. The following map identifies the problem address in I/O space.
I/O
0000h _________
| |
| Valid |
001Fh| |
0020h|---------|
| Invalid |
004Fh|---------|
0050h| |
| Valid |
| |
FFFFh|_________|
C5X I/O Space Map
Work around:
Avoid using the I/O space port addresses 20h to 4Fh.
WILL BE FIXED IN LATER REVISION
Problem 2: On the TDM port, the TADD of an empty slot drives low.
According to the User's Guide, an empty slot is defined by the
following two cases: 1) when no device has TCSR (TDM Channel Select
Register) configured to transmit in that slot (i.e., no 1's in TCSR).
2) when the slot is configured to transmit, but the TDXR (TDM Data
Transmit Register) has been writted a new data for transmit.
Typically, the TADD line should be in high impedance for an empty
slot. However, the TADD line is pulled low internally in the second
case mentioned above.
Work around:
If the high impedance is expected on TADD, put 0's in the
corresponding bits in the TCSR.
WILL BE FIXED IN LATER REVISION
Problem 3: When the TDM port is reset, external TFRM and TCLK may
corrupt the TDAT line.
After the TDM serial port was reset by XRST, the data in the first
several frames are shifted sometimes. This happens when the XRST and
the external TFRM pulse occur simultaneously and on the falling edge
of TCLK (see figure below).
__ __ __ __ __ __ __ __
TCLK __| |__| |__| |__| |__| |__| |__| |__| |__
_________________ __________________________
XRST |_____|
_______________
TFRM _____________| |_____________________
Work around in software:
For the normal software reset, pull the TRAD register to check the
current slot (bits 13-11) then reset the TDM port after first 2 slots
(such as slot 4). This will prevent the XRST and external TFRM
occurring simultaneously. In the IDLE2 mode, the device will freeze
the status of TDM port and continue after coming out of the power
down mode. Thus the TCSR has to be cleared before it get into the
IDLE2 mode. Otherwise the slot counter will be corrupted after
processor wakes up. Since the TCSR will not update until next frame,
it should clear a frame before IDLE2 executes. Wait for second TFRM
pulse after the processor comes out of IDLE2 mode to initialize TCSR.
Then reset the TDM port after first 2 slots. Following is a simple
example code to reset TDM port at slot 4.
SPLK #0h,TCSR ; clear TCSR before reset TDM port
RPT #lk ; waif for one more frame to update
the
NOP ; the TCSR. The lk should equal the
frame's
; period.
********************************************************
* Ready to reset TDM port or step into IDLE2 mode *
********************************************************
; IDLE2 ; get into IDLE2 mode
CALL TDMINIT ; or reset TDM port
.
.
.
TDMINIT:
; RPT #lk ; If comes out of IDLE2 mode, wait
for
; NOP ; 2nd TFRM pulse
CHK: LAMM TRAD ; Load TRAD Reg to chek bit 13-11
for
OR #3800h ; current slot information.
SUB #2000h ; If it is slot 4 then reset TDM
port
BCND CHK,NEQ
SPLK #0039h,TSPC ; put TDM port in reset
SPLK #00f9h,TSPC ; pull TDM port out of reset
RET
WILL BE FIXED IN LATER REVISION
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