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GM7HUD > SIX 22.12.05 01:22l 78 Lines 4505 Bytes #999 (0) @ WW
BID : 493158GM7HUD
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Subj: CB to 6m conversion 2
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Sent: 051221/2224z 71791@GB7ESX.#31.GBR.EU $:493158GM7HUD [Witham, Esx]NNA V3.1
*CB TO SIX METRES* Part2 - The PLL Frequency Synthesizer
By Shawn Baris ZR1EV
PO BOX 212
Brackenfell
7561
Republic of South Africa
*Anyone is free to use the following information for private use on the
provision that it is not used for commercial purposes . Permission is
granted by the author , ZR1EV , to publish and or distribute all or part of
the following on the condition that recognition is given to the author . In
the case of it being used in a newsletter or magazine , a copy of the
aforementioned should be sent to the above adress.*
For the purposes of this discussion , I will assume the following :(1)That
you have a working knowlege of RF circuitry and techniques .(2)That you
have the essential tools to do such a conversion . (3) Basic RF test
equipment .(4) The set you plan to convert is fully functional .(5)The set
is already fitted with a 40-channel selector switch .(6)That you have the
service / workshop manual of your rig .
The chassis I will be discussing is the UNIDEN PTBM048AOX -chassis fitted
to a number of CB rigs parading under different brand names . It is a
single conversion radio on SSB and double conversion on AM , based on the
popular PLL02A PLL chip , and has the Mitsubishi 2SC2166 and 2SC1969 in the
TX lineup . Some versions of this rig operated in the "C" band (29MHz
Marine) and had a diode matrix , six position channel switch , and could be
set to step in 12.5 kHz increments . In addition , these units also had a
"piggy-back" pcb fitted near the VCO , containing a 12.800 MHz oscillator .
These sets should be changed back to the original 27 Mhz configuration and
tested before any modifications are attempted .
The PLL02A(G) chip is quite remarkable in that it contains practically all
the components needed for a Pll synthesizer, except the VCO , of course .
The chip sports a 9-bit binary divide-by-N-counter , a phase comparator
with lock detect o/p (pin6) , and a fixed divider of either "divide-by-1024
or divide-by-2048" , selectable at pin 4 . In this application , a 10.240
Mc oscillator feeds into this fixed divider at pin3 , and when pin4 is left
o/c (logic1), will divide this signal by 1024 , resulting in 10kc , which
will be your synthesizer "step" . (If pin4 is tied to ground -logic0- the
fixed divider will now divide by 2048 , giving you a 5kc "step") DO NOT
change the 10.240 frequency . The output of that oscillator is also used in
the AM reciever section for the conversion of the 10.695 IF down to 455kc .
(10.695 - 10.240 = 0.455) !
At first glance , it seems as if the chip might be able to cover over
5MHz in one go (512 binary combinations at 10kc cannel spacing),but when
one has a good look at the spec sheet , the maximum frequency allowed into
the divide-by-N counter is limited to 3.5 MHz . So , at 10kc channel
spacing , the divide-N binary number of about 350 should not be exceeded to
ensure that the chip runs within it's specs . This is the main reason that
the mixer xtal (X1) 10.0525 MHz has to be changed .
IC2 functions as both the VCO and as a mixer (C3001/TA7310P) . The
interesting thing about this mixer is that it has two inputs (f1 and f2) ,
and two outputs (f1+f2 and f1-f2) . The difference output is taken off pin9
and the sum output is taken from pin6 . The difference output is fed into
the divide-by-N counter input , and the sum output is filtered and is used
as the Local Oscillator signal . X1 (10.0525) and Q3 make up the oscillator
and doubler stage .
As an example , channel 19 (27.185) , the VCO will run at 17.775 , mixed
by the output of the doubler 20.105 by IC2 and will produce two outputs :
the sum output, 37.880 and the difference output , 2.330 . The 2.330 goes
into the divide-by-N counter , where it is divided according to the value
in binary applied to pin7 (MSD) to pin15 (LSD) , in this case a value of
divide by 233 . The result of this division is 10kc , where it gets
"compared" to the 10kc "reference" frequency from the divide-by-1024 fixed
divider chain by the Phase comparator . The output from this "charge pump"
is fed to a LPF where the "error" is filtered to DC , so that it can be
used to either force the VCO frequency up or down untill there is no error.
The loop is now "locked" and pin6 will go to logic1 (5.4V) . The PLL (Phase
Locked Loop) .
To be continued...
vy73 de Shawn ZR1EV JF96ic
73 de Andy GM7HUD
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